Combinatorial mathematics; proceedings of the second by D.A. Holton

By D.A. Holton

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By integrating a few other components, an MPEG-2 decoder can be implemented on a single chip. The architecture of the D30V core is shown in Figure 11. There are three execution units in the D30V processor core: a memory unit, an integer unit, and a branch unit (inside the instruction decode unit). In addition to program sequencing control, the memory unit is also able to crunch data in its ALU and shifter. It supports several data types from byte (signed and unsigned) to 64-bit word. Its load and store instructions can operate on multiple operands using packing and unpacking.

In addition to the local interconnect network, there are also four global buses for forwarding data between stripes that are not next to each other. Evaluation of certain multimedia computing kernels shows a speedup factor of 11–190 over a 330-MHz UltraSPARC-II. The Cheops imaging system is a stand-alone unit for acquisition, processing, and display of digital video sequences and model-based representations of moving scenes [67]. Instead of using a number of general-purpose microprocessors and DSPs to achieve the computation power for video applications, Cheops abstracts out a set of basic, computationally intensive stream operations required for real-time performance of a variety of applications and embodies them in a compact, modular platform.

P Rubinfeld, R Rose, M McCallig. Motion Video Instruction Extensions for Alpha, White Paper. Hudson, MA: Digital Equipment Corporation, 1996. 18. MIPS Technologies, Inc. pdf, 1997. 19. T Komarek, P Pirsch. Array architectures for block-matching algorithms. IEEE Trans. Circuits Syst 36(10):1301–1308, 1989. 20. M Yamashina et al. A microprogrammable real-time video signal processor (VSP) for motion compensation. IEEE J Solid-State Circuits 23(4):907–914, 1988. 21. H Fujiwara et al. An all-ASIC implementation of a low bit-rate video codec.

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