By Dave Mussell
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Use of this cell design, with appropriate signals supplied to the Mode input of each cell, will result in a component that supports the SAMPLE, PRELOAD, EXTEST, and INTEST instructions. As will be discussed in Clause 11, other cell designs are possible that meet the requirements of this standard for different sets of instructions. For example: a) b) c) R2 may be either a flip-flop (as shown) or a latch. , the cells at system input pins. The lower input to M2 would in such cases be fed directly from the output of R1.
In addition, fault isolation of the board-level serial test data path shall be supported. This is achieved by loading a constant binary “01” pattern into the least significant bits of the instruction register at the start of the instruction-scan cycle. The inclusion of the optional design-specific data inputs to the instruction register allows key data signals within the device to be examined at the start of testing, with future test actions potentially depending on the design-specific information gathered.
When the BYPASS instruction is selected, the operation of the test logic shall have no effect on the operation of the on-chip system logic. 1 b). 2 Description The BYPASS instruction can be entered by holding TDI at a constant high value and completing an instruction-scan cycle. The demands on the host test system consequently are reduced in cases where access is required, say, to only chip 57 on a 100-chip board. In this case, the overall instruction pattern that shall be shifted into the design consists of a background of 1s with a small field of specific instruction data.